As explained in detail later, a "configurable logic element" (also referred to herein as a logic element) is a combination of devices which are capable of being electrically interconnected by switches operated in response to control bits to form any one of a plurality of logical functions.
Each configurable logic element (CLE) can include all the circuit elements necessary to provide one or more of the functions provided by an AND gate, flip flop, latch, inverter, NOR gate, exclusive OR gate, and combinations of these functions to form more complex functions. The particular function to be carried out by a configurable logic element is determined by control signals applied to the configurable logic element from control logic. Depending on the control signals, the configurable logic element can function as an AND gate, an OR gate, a NOR gate, a NAND gate or an exclusive OR gate or any one of a number of other logic elements without any change in physical structure. The control logic stores and generates control signals which control the configuration of each configurable logic element.
The control logic is typically formed integrally with and as part of the integrated circuit chip containing the configurable logic element. However, if desired the control information can be stroed and/or generated outside this integrated circuit and transmitted through pins to the configurable logic element.
In general, a given set of control signals is transmitted to one configurable logic element to control the configuration of that configurable logic element. The control logic is thus arranged to provide any one set of a plurality of sets of control bits to each configurable logic element on the chip. The actual set of control bits provided to each configurable logic element on the integrated circuit chip depends on the function to be carried out by the integrated circuit chip or by each configurable logic element on the chip. The configuration of each logic element on the chip is determined by the intended function of the total chip and by the intended formation of that configurable logic element as part of the chip.
A configurable logic array (CLA) comprises a plurality of CLEs, each having one or more input leads and one or more output leads, a set of access junctions for each input lead and for each output lead, and a general interconnect structure. The general interconnect structure comprises a plurality of general interconnect leads and a plurality of general interconnect junctions. The general interconnect structure has the property that for each lead in the general interconnect structure, there is a programming of the general interconnect junctions which connects the given general interconnect leads to one or more other general interconnect leads by means of a general interconnect junction. An access junction is a programmable junction for connecting a general interconnect lead to an input lead of a CLE or for connecting an output lead of the CLE to a general interconnect lead.
A CLA has the property that there is always a programming of the junctions (both access and general interconnect) so that a given output lead of a given CLE within the CLA can be connected to a given input lead of any other CLE within the CLA.
The junctions in the general interconnect structure and the access junctions are programmed by control signals generated by the control logic described above. A selection of control signals to configure each CLE in a CLA together with a selection of control signals to configure the access junctions and the junctions of the general interconnect structure results in one configuration of the CLA.
Frequently, when interconnecting logic elements in a configurable logic array, the access junctions and the junctions of the general interconnect structure are programmed so that the output of one logic element is only connected to one or two other logic elements. If the logic elements that are interconnected are physically close together (and they typically will be placed that way to facilitate interconnecting), I have discovered that a significant amount of general interconnect structure can be eliminated if special interconnect is provided which allows selected logic elements to be interconnected, i.e., the special interconnect reduces the utilization of the general interconnect structure provided may be reduced, thus reducing die size. Also, the speed of signals through this special interconnect will be improved since the number of junctions and the amount of capacitance on the path will be reduced. This type of interconnect is particularly useful when implementing MSI type functions, e.g., shift registers and counters, where adjacent logic elements must be interconnected.